Join WDL Systems and ADLINK Technology at PCB Carolina in Raleigh! Find us at Table # 7 in the McKimmon Convention Center on Wednesday, November 12.
PCB Carolina 2025
ADLINK Technology will present two technical sessions on Computer-On-Module (COM) technology. These presentations are ideal for engineers, students, and contract manufacturers who want to include compute power or AI in their design without reinventing the wheel.
Session 5C (2:00pm - 3:00pm): Inside the Module: State-of-the-Art Advances in Computer-on-Module Technology
Session 5D (3:30pm - 4:30pm): From Module to Market: A Practical Design-In Roadmap for Custom Computer-on-Module Carrier Boards
COMs help engineers cut costs and create future-proof designs by decreasing complexity, speeding up time-to-market, and maximizing scalability. ADLINK has played a key role in advancing and standardizing COMs for over two decades. As leaders in consortiums like PICMG and SGET, ADLINK has helped define everything from early COM industry standards to the advanced modules that drive modern Edge AI and other intelligent computing applications.
Session 5C (2:00pm - 3:00pm): Inside the Module: State-of-the-Art Advances in Computer-on-Module Technology
Presentation Abstract:
Computer-on-Module platforms have evolved from “processor mezzanines” into miniature HPC nodes that now rival 1U servers. This talk surveys the technical frontier, focusing on the new COM-HPC and next-gen COM Express pin-outs that enable:
- I/O bandwidth: 400-pin connectors supporting 32 GT/s PCIe Gen 5 today and a clear path to Gen 6/7 in the same footprint.
- Compute density: 24-core hybrid Intel® architectures, integrated AI/VNNI engines, and up to 128 GB DDR5 on-module.
- High-speed networking: Native 10/25/100 GbE KR lanes and time-sensitive-networking (TSN) hooks for deterministic edge workloads.
- Scalability & serviceability: Module/carrier separation that lets OEMs refresh CPUs every few years while preserving costly compliance artifacts (EMC, safety, FDA, etc.).
- Thermal & power design: Real-world data on cooling 65 W+ processors in fanless enclosures—heat-spreader options, vapor chambers, and SIM thermal simulation tips.
Attendees will leave with a roadmap of which COM standards best fit next-generation edge-AI, defense, medical, and industrial automation designs—and what trade-offs to expect around signal integrity, PCB stack-up, and long-term availability. No product pitches—just practical engineering insight from 25 years of module evolution.
Presenter:
Stone Shih has worked across the industrial computing ecosystem for 28 years, providing him with a comprehensive perspective on COM technology evolution. With a B.S. in Mechanical Engineering from National Taiwan University of Science and Technology and an MBA from The Chinese University of Hong Kong, Stone has held roles spanning sales engineering, product management, and business unit leadership at Advantech, AAEON, NEXCOM, and EverFocus.
As Director of AAEON's Industrial System Division, Stone directed product development roadmaps for networking, security, and industrial automation platforms, leading the business unit to top performance recognition. At AAEON USA, he grew the systems division by 28% while helping customers implement modular architecture strategies—balancing performance requirements with thermal constraints, compliance preservation, and long-term availability concerns.
Stone's experience encompasses the practical trade-offs that define COM platform selection: signal integrity considerations for high-speed interfaces, PCB stack-up decisions, thermal management in constrained environments, and the business implications of module/carrier separation for multi-year product lifecycles. He has worked with engineering teams across medical devices, defense systems, transportation, and industrial automation—vertical markets where design decisions have significant compliance and reliability implications.
This session provides an engineering-focused analysis of current COM standards—COM-HPC and next-generation COM Express—examining technical capabilities (PCIe Gen 5 bandwidth, 24-core hybrid architectures, integrated AI engines, high-speed networking) alongside real-world implementation considerations. Stone will address practical questions around thermal design for high-TDP processors, signal integrity requirements, and platform selection criteria for specific application domains.
Stone is bilingual in English and Mandarin.
Session 5D (3:30pm - 4:30pm): From Module to Market: A Practical Design-In Roadmap for Custom Computer-on-Module Carrier Boards
Picking a COM is only the first step—the real engineering begins when you marry that module to a purpose-built carrier. Drawing on two decades of hands-on design-in support, this session maps out a repeatable workflow that keeps projects on schedule and within budget:
- Requirements capture: Translating functional specs into connector-pin budgets, power envelopes, and PCB layer counts.
- Reference-design leverage: How to mine the PICMG COM-HPC Carrier Design Guide and proven schematics to shortcut risk.
- Signal-integrity & stack-up: Routing PCIe Gen 5, 25-GbE-KR, and USB4 while meeting ∆-T targets; choosing loss-optimized laminates.
- Power-/Thermal-co-design: DC-DC stage selection, load-step validation, mechanical keep-out for heat spreaders, and CFD checkpoints.
- Firmware & BSP hand-off: Secure boot, board-ID EEPROM, carrier-specific ACPI tables, and automated regression test hooks.
- Design for X: Manufacturability, test, compliance, and—crucially for CMs—how to structure DFX reviews so issues surface before Gerber release.
Real case studies illustrate pitfalls (e.g., marginal eye diagrams on 30-inch PCIe lanes) and the quick wins that shave weeks off EVT. Engineers, students, and contract manufacturers will gain a clear blueprint for turning any COM into a robust, certifiable product—whether the target is a handheld medical scanner or a ruggedized radar processor.
Presenter:
Dr. Serchen Chang brings over 20 years of embedded systems development experience to a session focused on the practical realities of COM carrier board design. With a Ph.D. in Electrical Engineering from National Cheng Kung University, Serchen has held hands-on engineering roles throughout his career—developing H.264/MPEG4 video codecs on DSP platforms, architecting ARM-based embedded systems, and leading R&D teams at AVerMedia, AVer Information, and LITEON Technology.
His background spans the full product development cycle: from initial requirements capture and schematic design through signal integrity validation, thermal management, firmware integration, and production ramp. At AVerMedia, his team developed an embedded surveillance platform that earned the 2007 CES Best Innovation Award. As Technical Product Manager supporting OEM/ODM customers across Japan and the U.S., he guided engineering teams through the carrier board design process—helping them navigate reference designs, resolve signal integrity issues, coordinate BSP hand-offs, and structure design-for-manufacturing reviews.
This session draws on Serchen's experience with real-world design challenges: managing PCIe Gen 5 signal integrity across extended trace lengths, validating power delivery under load transients, optimizing thermal solutions within mechanical constraints, and coordinating the firmware dependencies that often become critical-path issues. Attendees will gain practical insight into proven workflows, common pitfalls, and design decisions that significantly impact schedule and budget.
Dr. Chang is also a FAA-certified Flight Instructor with 1,600+ flight hours.
PCB Carolina is North Carolina's premier electronics show with over 100 exhibitors and 17 technical sessions by industry leaders. Attendance is completely free and includes a hot breakfast, a full lunch buffet with brisket and fried chicken, an evening reception, and door prizes.
What to Expect
Over 100 Exhibits and 16 Technical Sessions
Breakfast, Lunch, and Evening Reception Provided
Over 200 Door Prizes, Grand Prizes awarded during Evening Reception
FREE to all Attendees
Date: November 12
Hours: 7:30am – 6:00pm
Location: NC State McKimmon Center, Raleigh, NC
1101 Gorman Street
Raleigh, NC 27606
Show Schedule
7:30am = Attendee Check-in opens, Breakfast Served
8:30am = Keynote Address
9:30am = Exhibitor space opens, First Technical Session Begins
11:00am = Second Technical Session begins
11:30am – 1:30pm = Lunch
2:00pm = Third Technical Session begins
3:30pm = Forth Technical Session begins
5:00pm = Evening reception
5:20pm = Grand Prize Drawings
6:00pm = Show Ends